1. Field of the Invention
The present invention relates to a high-speed floating-point normalizing circuit which can be easily incorporated in an integrated circuit.
2. Description of Related Art
In general, a floating-point arithmetic operation needs a floating-point normalization. FIG. 1 shows one example of the conventional floating-point arithmetic circuit which has a floating-point normalizing circuit. As shown in FIG. 1, the floating-point normalizing circuit 10 includes a comparator (CMP) 12 receiving two multi-bit numbers A and B to determine which is larger, A or B. This comparator 12 controls a multiplexer (MUX) 14 which also receives the two input numbers A and B, so that the multiplexor 14 outputs a larger one of the two input numbers to a shift and count circuit (SAC) 16. This SAC circuit 16 leftwardly shifts the input number until the shifted number has a nonzero leftmost digit, i.e., "1" at the most significant digit, and at the same time the SAC circuit 16 counts the amount of the shift, Thus, the SAC circuit 16 outputs the result of the count to an encoder 18, which is in turn converts the counted value into an exponent data in a floating-point representation. Further, the output of the SAC circuit 16 is supplied to a pair of shifters 20 and 22 which receive the input numbers A and B, respectively, so that the respective shifters shift the respective input numbers the same amount indicated by the SAC circuit 16. The two numbers A and B thus shifted are outputted from the respective shifters 20 and 22 to a processing unit 24, which in turn executes a designated arithmetic operation to the two input numbers so as to output the result of the arithmetic operation as a fraction or mantissa in a floating-point representation.
As seen from the above, the conventional floating-point normalizing circuit includes three different circuits, i.e., the comparator, the multiplexor and the shift and count circuit, and therefore, the normalizing circuit is inevitably complicated. In addition, the normalizing output is generated through the three sequential steps, i.e., the comparison, the selection and the shift, and so, the operation speed is not so fast. Therefore, the conventional floating-point normalizing circuit is not suitable for a high speed operation circuit in the form of an integrated circuit.